Figure 9-35: Timer E Capture Operation: 32-Bit Cascade Operation Mode - NEC V850E/CA1 ATOMIC Preliminary User's Manual

Figure 9-35: Timer E Capture Operation: 32-Bit Cascade Operation Mode

(When CMSEmn Register's TB1Ex Bit = 1, TB0Ex Bit = 1, CCSEx Bit = 0, LNKEx Bit = 0,
BFEEx Bit = Arbitrary, EEVEx Bit = 1, and CSCEn Register's SEVEx Bit = 0)
f
CLK
TCOUNTE0 =
TCOUNTE1
FFFEH
CNT (TB0)
CNT (TB1)
Note 1
CASC
MUXTB0
MUXTB1
MUXCNT
TB1
ED1
CAPTURE_S
CAPTURE_P
READ_ENABLE_P
CVSExn register
CVPExn register
Notes: 1. TBASE1n performs count operation when, in the 32-bit mode, CASC (CNT = MAX. for
TBASE0n) is input to TBASE1n and the rising edge of CTC is detected.
2. If an event occurs during this timing, it is ignored.
3. CPU read access is not performed in this timing (wait status).
Remarks: 1. f = f
CLK CPU
2. CAPTURE_P:
CAPTURE_S:
CASC:
CNT (TB0):
CNT (TB1):
ED1:
MUXCNT:
MUXTB0:
MUXTB1:
READ_ENABLE_P: Read timing of CVPExn register
TB0, TB1:
TCOUNTE0:
TCOUNTE1:
3. x = 1 to 4
m = 12, when x = 1 or 2
m = 34, when x = 3 or 4
n = 0 to 2
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Chapter 9 Timer / Counter (Real Time Pulse Unit)
FFFFH
1234H
FFFEH 1234H FFFFH 1234H FFFFH 1234H
TB0 TB1 TB0 TB1 TB0 TB1
Undefined
Undefined
: Base clock
Capture trigger signal of main capture register
Capture trigger signal of sub capture register
TBASE1n count signal in 32-bit mode
Count value of time baser TBASE0n
Count value of time baser TBASE1n
Capture event signal input from edge selection circuit
Count value to sub-channel x
Multiplex signal of TBASE0n
Multiplex signal of TBASE1n
Time base TBASE0n, TBASE1n
Timer TMEn count enable signal input of time base TBASE0n
Timer TMEn count enable signal input of time base TBASE1n
Preliminary User's Manual U14913EE1V0UM00
0000H
FFFFH 1234H 0000H 1235H 0000H 1235H
TB0 TB1 TB0 TB1 TB0 TB1
Note 2
Enable the next capture
0000H
Note 3
0001H
1235H
0000H 1235H 0001H 1235H 0001H
TB0 TB1 TB0 TB1 TB0 TB1
Note 2
0001H
1235H
Note 3
1235H 0001H
TB0
1235H