Interrupt Control Register (Xxicn) - NEC V850/SA1 mPD703015 Preliminary User's Manual

5.3.4 Interrupt control register (xxICn)

An interrupt control register is assigned to each maskable interrupt and sets the control conditions for each mas-
kable interrupt request.
The interrupt control register can be read/written in 8- or 1-bit units.
After reset: 47H R/W
Symbol 7
xxICn xxIFn xxMKn
xxIFn
0 Interrupt request not issued
1 Interrupt request issued
xxMKn
0 Enables interrupt processing
1 Disables interrupt processing (pending)
xxPRn2 xxPRn1
0
0
0
0
1
1
1
1
Note Automatically reset by hardware when interrupt request is accepted.
Remark xx : Identification name of each peripheral unit (WDT, P, WTI, TM, CS, SER, SR, ST, AD,
DMA, WT)
n : Peripheral unit number (0 to 6)
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Figure 5-10. Interrupt Control Register (xxICn) Format
Address: FFFFF100H-FFFFF13AH
6 5 4
0 0
Interrupt request flag
Interrupt mask flag
xxPRn0
0 0 Specifies level 0 (highest)
0 1 Specifies level 1
1 0 Specifies level 2
1 1 Specifies level 3
0 0 Specifies level 4
0 1 Specifies level 5
1 0 Specifies level 6
1 1 Specifies level 7 (lowest)
3 2 1
0 xxPRn2 xxPRn1
Note
Interrupt priority specification bit
0
xxPRn0
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