14.4 Operation of DMA Controller
14.4.1 Operation procedure
<1> The DMA controller is enabled to operate when DENn = 1. Before writing the other registers, be sure to set
DENn to 1. Use 80H to write with an 8-bit manipulation instruction.
<2> Set an SFR address, a RAM address, the number of times of transfer, and a transfer mode of DMA transfer
to the DSAn, DRAn, CBCn, and DMCn registers.
<3> The DMA controller waits for a DMA trigger when DSTn = 1. Use 81H to write with an 8-bit manipulation
instruction.
<4> When a software trigger (STGn) or a start source trigger specified by IFCn3 to IFCn0 is input, a DMA transfer
is started.
<5> Transfer is completed when the number of times of transfer set by the DBCn register reaches 0, and transfer
is automatically terminated by occurrence of an interrupt (INTDMAn).
<6> Stop the operation of the DMA controller by clearing DENn to 0 when the DMA controller is not used.
CHAPTER 14 DMA CONTROLLER
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