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4.7 Idle State Insertion Function
To facilitate interfacing with low-speed memory devices, an idle state (TI) can be inserted into the current bus cycle
after the T2 state in order to meet the data output float delay time (t
block. The bus cycle following the T2 state starts after the idle state is inserted.
Specifying insertion of the idle state is programmable by setting the bus cycle control register (BCC).
Immediately after the system reset is cancelled, idle state insertion is automatically programmed for all memory
blocks.
The idle state is inserted only if the read cycle is followed by a write cycle.
(1) Bus cycle control register (BCC)
This register can be read/written in 16-bit units.
15
14
13
BCC
BC71
BC70
BC61
BC60
Memory
7
6
block
Bit Position
Bit Name
15 to 0
BCn1,
BCn0
(n = 7 to 0)
Cautions 1. The internal ROM area, internal RAM area and internal peripheral I/O area are not subject to
insertion of an idle state.
2. Write to the BCC register after reset, and then do not change the set value. Also, do not
access an external memory area other than the one for this initialization routine until the
initial setting of the BCC register is complete.
external memory area whose initialization is complete.
CHAPTER 4 BUS CONTROL FUNCTION
12
11
10
9
8
7
BC51
BC50
BC41
BC40
BC31
5
4
3
Bus Cycle
Specifies insertion of an idle state in memory block n.
BCn1
BCn0
0
0
0
1
1
Optional
User's Manual U12688EJ4V0UM00
) on memory read accesses for each memory
DF
6
5
4
3
2
1
BC30
BC21
BC20
BC11
BC10
BC01
2
1
0
Function
Idle State in Memory Block n
Not inserted
Inserted
RFU (Reserved)
However, it is possible to access an
0
Address
After reset
BC00
FFFFF062H
5555H
117
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