Figure 412. Asynchronous Wait During A Read Access; Figure 413. Asynchronous Wait During A Write Access - ST STM32F205 series Reference Manual

Advanced arm-based 32-bit mcus

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Table of Contents

1. NWAIT polarity depends on WAITPOL bit setting in FSMC_BCRx register.

1. NWAIT polarity depends on WAITPOL bit setting in FSMC_BCRx register.

Figure 412. Asynchronous wait during a read access

address phase

address phase

Flexible static memory controller (FSMC)

Memory transaction

data setup phase

Memory transaction

data setup phase

data driven by FSMC

RM0033 Rev 8

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