Table 215. Cortex ® -M3 Ahb-Ap Registers; Sw-Ap Registers - ST STM32F205 series Reference Manual

Debug support (DBG)
32.8.6

SW-AP registers

Access to these registers are initiated when APnDP=1
There are many AP Registers (see AHB-AP) addressed as the combination of:
• The shifted value A[3:2]
•
The current value of the DP SELECT register
32.9 AHB-AP (AHB access port) - valid for both JTAG-DP
and SW-DP
Features:
•
System access is independent of the processor status.
•
Either SW-DP or JTAG-DP accesses AHB-AP.
•
The AHB-AP is an AHB master into the Bus Matrix. Consequently, it can access all the
data buses (Dcode Bus, System Bus, internal and external PPB bus) but the ICode
bus.
•
Bitband transactions are supported.
•
AHB-AP transactions bypass the FPB.
The address of the 32-bits AHP-AP resisters are 6-bits wide (up to 64 words or 256 bytes)
and consists of:
c)
d)
The AHB-AP of the Cortex
Address
offset
0x00
0x04
0x0C
0x10
0x14
0x18
0x1C
0xF8
0xFC
Refer to the Cortex
1330/1378
Bits [7:4] = the bits [7:4] APBANKSEL of the DP SELECT register
Bits [3:2] = the 2 address bits of A[3:2] of the 35-bit packet request for SW-DP.
®
-M3 includes 9 x 32-bits registers:
Table 215. Cortex
Register name
AHB-AP Control and Status
Word
AHB-AP Transfer Address
AHB-AP Data Read/Write
AHB-AP Banked Data 0
AHB-AP Banked Data 1
AHB-AP Banked Data 2
AHB-AP Banked Data 3
AHB-AP Debug ROM Address Base Address of the debug interface
AHB-AP ID Register
®
-M3 r2p0 TRM for further details.
®
-M3 AHB-AP registers
Configures and controls transfers through the AHB
interface (size, hprot, status on current transfer, address
increment type
Directly maps the 4 aligned data words without rewriting
the Transfer Address Register.
RM0033 Rev 8
RM0033
Notes
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