ST STM32F205 series Reference Manual page 1366

Revision history
Date
04-Feb-2015
1366/1378
Table 224. Document revision history (continued)
Version
PWR
Updated Table 7: Low-power mode summary
as entry condition.
Added Section : Entering low-power mode
power mode.
Updated Section : Entering Sleep
mode, Table 8: Sleep-now
Updated Section : Entering Stop
and Table 10: Stop
Updated Section : Entering Standby
mode and Table 11: Standby
RCC
Updated caution note applying to PLLN in
configuration register
Changed bits 25 to 31 access type to 'r' and bit 24 (RMVF) to 'rt_w'
in Section 5.3.21: RCC clock control & status register (RCC_CSR)
DMA
Updated Section 9.3.7: Pointer incrementation
Single and burst
Updated FTH[1:0] description in
control register (DMA_SxFCR) (x =
7
ADC
Updated Section 10.3.10: Discontinuous
DCMI
Updated Section 12.4: DCMI clocks
physical interface
TIM1/8
Updated CCPC definition in
register 2 (TIMx_CR2)
TIM2 to TIM5
Replaced IC2S by CC2S. Updated
capture/compare channel (channel
TIM9 to TIM14
Added Section 15.5.2: TIM10/11/13/14 Interrupt enable register
(TIMx_DIER). Updated
Added Section 15.5.2: TIM10/11/13/14 Interrupt enable register
(TIMx_DIER).
WDGLS
Update note in
kHz (LSI).
RM0033 Rev 8
Changes
mode,
and Table 9:
mode,
mode.
mode,
mode.
(RCC_PLLCFGR).
transfers.
Section 9.5.10: DMA stream x FIFO
0..7).
and
Section 13.4.2: TIM1 and TIM8 control
Figure 140: Output stage of
1).
Table 63: TIMx internal trigger
Table 69: Min/max IWDG timeout period (in ms) at 32
RM0033
to add Return from ISR
and Section : Exiting low-
Section : Exiting Sleep
Sleep-on-exit.
Section : Exiting Stop mode,
Section : Exiting Standby
Section 5.3.2: RCC PLL
and Section 9.3.11:
mode.
Section 12.5.2: DCMI
connection.