ST STM32F205 series Reference Manual page 1361

RM0033
Date
05-Nov-2012
Table 224. Document revision history (continued)
Version
PWR:
Updated V
DDA
supply overview. Updated case of no external battery in
Section 4.1.2: Battery backup
RCC:
Updated System clock frequency in
Figure 11: Frequency measurement with TIM5 in Input capture
mode. Updated HSITRIM[4:0] in
register (RCC_CR).
GPIOs:
Updated debug pins input pull-up/pull-down status after reset in
Section 6.3.1: General-purpose I/O
Interrupts and events:
Updated number of maskable interrupt in
features.
DMA:
Updated direct mode description in
Updated direct mode description in
mode, and /Section : Memory-to-memory
5
ADC:
Changed ADCCLK frequency to 30 MHz in
wise programmable sampling
temperature.
Added recovery from ADC sequence in
DMA and Section 10.8.2: Managing a sequence of conversions
without using the
TIM1 to TIM8:
Updated 16-bit prescaler range in
features.
Updated update event generation in
Section : Downcounting mode
and in Section 13.3.3: Repetition
Updated OC1 block diagram in
capture/compare channel (channel 1 to
Updated Section 13.3.6: Input capture
Updated bits that control the dead-time generation in
Section 13.3.11: Complementary outputs and dead-time
Updated ways to generate a break in
break function.
OCxREF changed to ETR in the example given in
Clearing the OCxREF signal on an external event
to ETRF in Figure 103: Clearing TIMx
RM0033 Rev 8
Changes
and V decoupling capacitor in
REF+
domain.
Figure 9: Clock tree
Section 5.3.1: RCC clock control
(GPIO).
Section 9.2: DMA main
Section : Memory-to-peripheral
time. Updated
DMA.
Section 13.2: TIM1 and TIM8 main
Section : Upcounting mode
in Section 13.3.2: Counter
counter.
Figure 93: Output stage of
mode.
Section 13.3.12: Using the
OCxREF.
Revision history
Figure 3: Power
and
Section 8.1.1: NVIC
features.
mode.
Section 10.5: Channel-
Section : Reading the
Section 10.8.1: Using the
modes,
3).
insertion.
Section 13.3.13:
and OCREF_CLR
1361/1378
and
1372