ST STM32F205 series Reference Manual page 1368

Revision history
Date
2-May-2018
1368/1378
Table 224. Document revision history (continued)
Version
Added Arm logo and notice in
and changed 'ARM' wordmark to 'Arm' in the whole document.
RCC
Changed OTG_HS_SCL into OTG_HS_ULPI_CK in
tree.
GPIOs
Changed definition of OSPEEDR bits in
output speed register (GPIOx_OSPEEDR) (x =
DMA
Changed bit 18 of DMS_SxCR to DBM in register bit map table.
Changed bit 20 from ACK to reserved in
and reset values.
ADC
Updated DMA mode 1 and DMA mode 3 description in
Multi ADC mode.
DAC
8
Replaced 4095 by 4096 in formula in
voltage.
TIM1 and TIM8
Updated Section 13.3.21: Debug
Added note related to slave clock in MMS bits of TMIx_CR2.
Extended TIMx_DMAR to 32 bits.
Changed TIMx_ARR reset value to 0xFFFF.
Updated Table 57: Output control bits for complementary OCx and
OCxN channels with break feature
Updated SMS bit description in TIMx_SMCR and added note related
to slave clock. Updated
TIM2 to TIM5
Added note related to the slave timer clock in
synchronization.
Updated SMS bit description in TIMx_SMCR and added note related
to slave clock.
Added note related to slave clock in MMS bits of TMIx_CR2.
Updated Section 14.4.11: TIMx prescaler
Changed TIMx_ARR reset value to 0xFFFF.
Changed TIMx_ARR reset value to 0xFFFF.
RM0033 Rev 8
Changes
Section 1: Documentation conventions
Section 6.4.3: GPIO port
Table 31: DMA register map
Section 11.3.5: DAC output
mode.
output state for MOE = 0.
Table 56: TIMx Internal trigger
Section 14.3.15: Timer
(TIMx_PSC).
RM0033
Figure 9: Clock
A..I).
Section 10.9:
connection.