ST STM32F205 series Reference Manual page 1354

Revision history
Date
15-Apr-2011
1354/1378
Table 224. Document revision history (continued)
Version
Updated OTP area in
Modified Section : Embedded
Changed f
MASTER
Modified DAC bus in
boundary addresses.
PWR:
Added note related to voltage regulator activation depending to
package in Section 4.1.3: Voltage
RCC:
Added note related to I2S PLL used as I2S input clock in
Section 5.2.3: PLL
Modified VCO output frequency for PLLN bit description in
Section 5.3.2: RCC PLL configuration register
GPIOs:
Removed RTF_AF1 and RTC_AF2 from system functions in
Section 6.3.2: I/O pin multiplexer and
Modified Section 6.3.13: Using the OSC32_IN/OSC32_OUT pins as
GPIO PC14/PC15 port pins
OSC_IN/OSC_OUT pins as GPIO PH0/PH1 port pins
3
TIMERS:
TIM1&TIM8: Updated example and definition of DBL bits in
Section 13.4.19: TIM1 and TIM8 DMA control register
Added example related to DMA burst feature and description of
DMAB bits in
transfer (TIMx_DMAR).
TIM2 to TIM5: added example and updated definition of DBL bits in
Section 14.4.17: TIMx DMA control register
example related to DMA burst feature and description of DMAB bits
in Section 14.4.18: TIMx DMA address for full transfer
(TIMx_DMAR).
IWDG:
Modified LSI clock frequency in
period (in ms) at 32 kHz (LSI)
WWDG:
Updated Section 18.2: WWDG main
Updated Section 18.3: WWDG functional description
paragraph related to counter reload using EWI interrupt.
Added Section : Advanced watchdog interrupt
Section 18.4: How to program the watchdog
RM0033 Rev 8
Changes
Section 2.3.3: Embedded Flash
bootloader.
to CK_INT in the whole document.
Table 1: STM32F20x and STM32F21x register
regulator.
configuration.
and Section 6.3.14: Using the
Section 13.4.20: TIM1 and TIM8 DMA address for full
Table 69: Min/max IWDG timeout
title and updated timeout values.
features.
RM0033
memory.
(RCC_PLLCFGR).
mapping.
(TIMx_DCR).
(TIMx_DCR). Added
to remove
featurein
timeout.