Flexible static memory controller (FSMC)
Bit No.
31-20
19
18:16
15
14
13
12
11
10
9
8
7
6
5-4
3-2
1
0
Bit
number
31:30
29-28
27-24
23-20
19-16
15-8
7-4
3-0
1278/1378
Table 187. FSMC_BCRx bit fields
Bit name
Reserved
CBURSTRW
CPSIZE
ASYNCWAIT
EXTMOD
WAITEN
WREN
WAITCFG
WRAPMOD
WAITPOL
BURSTEN
Reserved
FACCEN
MWID
MTYP[0:1]
MUXEN
MBKEN
Table 188. FSMC_BTRx bit fields
Bit name
Reserved
0x0
ACCMOD
0x2
DATLAT
0x0
CLKDIV
0x0
BUSTURN
Time between NEx high to NEx low (BUSTURN HCLK)
Duration of the second access phase (DATAST HCLK cycles) for
DATAST
read accesses.
ADDHLD
Don't care
Duration of the first access phase (ADDSET HCLK cycles) for read
accesses.
ADDSET[3:0]
Minimum value for ADDSET is 0.
RM0033 Rev 8
0x000
0x0 (no effect on asynchronous mode)
0x0 (no effect on asynchronous mode)
Set to 1 if the memory supports this feature. Otherwise keep
at 0.
0x1
0x0 (no effect on asynchronous mode)
As needed
Don't care
0x0
Meaningful only if bit 15 is 1
0x0
0x1
0x1
As needed
0x2 (NOR Flash memory)
0x0
0x1
Value to set
Value to set
RM0033
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