ST STM32F205 series Reference Manual page 1311

RM0033
Bits 31:24 MEMHIZx[7:0]: Common memory x databus HiZ time
Bits 23:16 MEMHOLDx[7:0]: Common memory x hold time
Bits 15:8 MEMWAITx[7:0]: Common memory x wait time
Bits 7:0 MEMSETx[7:0]: Common memory x setup time
Attribute memory space timing registers 2..4 (FSMC_PATT2..4)
Address offset: 0xA000 0000 + 0x4C + 0x20 * (x – 1), x = 2..4
Reset value: 0xFCFC FCFC
Each FSMC_PATTx (x = 2..4) read/write register contains the timing information for PC
Card/CompactFlash or NAND Flash memory bank x. It is used for 8-bit accesses to the
attribute memory space of the PC Card/CompactFlash or to access the NAND Flash for the
last address write access if the timing must differ from that of previous accesses (for
Ready/Busy management, refer to
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ATTHIZ[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the
start of a PC Card/NAND Flash write access to common memory space on socket x. Only
valid for write transaction:
0000 0000: 1 HCLK cycle
1111 1110: 255 HCLK cycles
1111 1111: Reserved
For NAND Flash read accesses to the common memory space, these bits define the
number of (HCLK+2) clock cycles during which the address is held after the command is
deasserted (NWE, NOE).
For NAND Flash write accesses to the common memory space, these bits define the
number of HCLK clock cycles during which the data are held after the command is
deasserted (NWE, NOE).
0000 0000: Reserved
0000 0001: 1 HCLK cycle for write accesses, 3 HCLK cycles for read accesses
1111 1110: 254 HCLK cycle for write accesses, 256 HCLK cycles for read accesses
1111 1111: Reserved
Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE,
NOE), for PC Card/NAND Flash read or write access to common memory space on socket
x. The duration for command assertion is extended if the wait signal (NWAIT) is active (low)
at the end of the programmed value of HCLK:
0000 0000: Reserved
0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT)
1111 1110: 255 HCLK cycles (+ wait cycle introduced by deasserting NWAIT)
1111 1111: Reserved.
Defines the number of HCLK (+1) clock cycles to set up the address before the command
assertion (NWE, NOE), for PC Card/NAND Flash read or write access to common memory
space on socket x:
0000 0000: 1 HCLK cycle
1111 1110: 255 HCLK cycles
1111 1111: Reserved
ATTHOLD[7:0]
Flexible static memory controller (FSMC)
Section 31.6.5: NAND Flash prewait
ATTWAIT[7:0]
RM0033 Rev 8
functionality).
9 8 7 6 5 4 3
ATTSET[7:0]
2 1 0
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