Table 209. Jtag Debug Port Data Registers - ST STM32F205 series Reference Manual

RM0033
32.6.3 Cortex
The TAP of the Arm
default one and has not been modified. This code is only accessible by the JTAG Debug
Port.
This code is 0x0BA00477 (corresponds to Cortex
32.6.4 Cortex
The Arm
mapped on the internal PPB bus at address 0xE00FF000_0xE00FFFFF.
This code is accessible by the JTAG Debug Port (4 to 5 pins) or by the SW Debug Port (two
pins) or by the user software.
32.7 JTAG debug port
A standard JTAG state machine is implemented with a 4-bit instruction register (IR) and five
data registers (for full details, refer to the Cortex
(TRM), for references, see
IR(3:0)
1111
1110
1010
®
-M3 TAP
® ®
Cortex -M3 integrates a JTAG ID code. This ID code is the Arm
®
-M3 JEDEC-106 ID code
® ®
Cortex -M3 integrates a JEDEC-106 ID code. It is located in the 4KB ROM table
Section

Table 209. JTAG debug port data registers

Data register
BYPASS
[1 bit]
IDCODE ID CODE
[32 bits] 0x0BA00477 (Arm
Debug port access register
This initiates a debug port and allows access to a debug port register.
– When transferring data IN:
Bits 34:3 = DATA[31:0] = 32-bit data to transfer for a write request
Bits 2:1 = A[3:2] = 2-bit address of a debug port register.
Bit 0 = RnW = Read request (1) or write request (0).
DPACC
– When transferring data OUT:
[35 bits]
Bits 34:3 = DATA[31:0] = 32-bit data which is read following a read
request
Bits 2:0 = ACK[2:0] = 3-bit Acknowledge:
010 = OK/FAULT
001 = WAIT
OTHER = reserved
Refer to
®
-M3 r2p0, see
®
-M3 r2p0 Technical Reference Manual
32.2).
®
®
Cortex
-M3 r2p0 ID Code)
Table 210 for a description of the A[3:2] bits
RM0033 Rev 8
Debug support (DBG)
Section 32.2).
Details
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®
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