Table 189. Fsmc_Bwtrx Bit Fields; Figure 408. Mode D Read Accesses - ST STM32F205 series Reference Manual

RM0033
Bit
number
31:30
29-28
27-24
23-20
19-16
15-8
7-4
3-0
Mode D - asynchronous access with extended address

Table 189. FSMC_BWTRx bit fields

Bit name
Reserved 0x0
ACCMOD 0x2
DATLAT Don't care
CLKDIV Don't care
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
Duration of the second access phase (DATAST+1 HCLK cycles for
DATAST
write accesses,
ADDHLD Don't care
Duration of the first access phase (ADDSET HCLK cycles) for write
accesses.
ADDSET[3:0]
Minimum value for ADDSET is 0.

Figure 408. Mode D read accesses

A[25:0]
NADV
NEx
NOE
NWE
High
D[15:0]
ADDSET
HCLK cycles
Flexible static memory controller (FSMC)
Memory transaction
ADDHLD
HCLK cycles
RM0033 Rev 8
Value to set
data driven
by memory
DATAST
HCLK cycles
ai15566
1279/1378
1316