Flexible static memory controller (FSMC)
The differences compared with mode1 are the toggling of NOE and the independent read
and write timings.
Bit
number
31-20
19
18:16
15
14
13
12
11
10
9
8
7
6
5-4
3-2
1272/1378
Figure 402. ModeA write accesses
A[25:0]
NBL[1:0]
NEx
NOE
NWE
D[15:0]
Table 181. FSMC_BCRx bit fields
Bit name
Reserved
0x000
CBURSTRW
0x0 (no effect on asynchronous mode)
CPSIZE
0x0 (no effect on asynchronous mode)
Set to 1 if the memory supports this feature. Otherwise keep at
ASYNCWAIT
0.
EXTMOD
0x1
WAITEN
0x0 (no effect on asynchronous mode)
WREN
As needed
WAITCFG
Don't care
WRAPMOD
0x0
WAITPOL
Meaningful only if bit 15 is 1
BURSTEN
0x0
Reserved
0x1
FACCEN
Don't care
MWID
As needed
MTYP[0:1]
As needed, exclude 0x2 (NOR Flash)
RM0033 Rev 8
Memory transaction
ADDSET
HCLK cycles
1HCLK
data driven by FSMC
(DATAST + 1)
HCLK cycles
Value to set
RM0033
ai15560
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