Figure 410. Multiplexed Read Accesses; Figure 411. Multiplexed Write Accesses - ST STM32F205 series Reference Manual

Flexible static memory controller (FSMC)
Muxed mode - multiplexed asynchronous access to NOR Flash memory
The difference with mode D is the drive of the lower address byte(s) on the databus.
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Figure 410. Multiplexed read accesses

Figure 411. Multiplexed write accesses

A[25:16]
NADV
NEx
NOE
NWE
AD[15:0]
ADDSET
HCLK cycles
Memory transaction
Lower address
ADDHLD
HCLK cycles
RM0033 Rev 8
1HCLK
data driven by FSMC
(DATAST + 1)
HCLK cycles
RM0033
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