After Power-Up And Configuration; After Turning On A Reference Clock To Rx Pll - Xilinx Virtex-6 FPGA User Manual

Chapter 4: Receiver
Table 4-55: Recommended Resets for Common Situations
Situation
After power up and
configuration
After turning on a reference
clock to RX PLL
After changing the reference
clock to RX PLL
After assertion/deassertion
of RXPOWERDOWN
RX rate change with RX
elastic buffer bypassed
RX rate change with RX
elastic buffer enabled
RX parallel clock source reset
After remote power up
Electrical idle reset
After connecting
(2)
RXN/RXP
After an RXBUFFER error
Before channel bonding
After changing channel
bonding mode on the fly
After PRBS error
After an oversampler error
After comma realignment
Notes:
1. The recommended reset has the smallest impact on the other components of the GTX transceiver.
2. It is assumed that RXN/RXP are connected simultaneously.

After Power-up and Configuration

The entire GTX RX is reset automatically after the configuration-provided
RXPLLPOWERDOWN is Low. The supplies for the calibration resistor and calibration
resistor reference must be powered up before configuration to ensure correct calibration of
the termination impedance of all transceivers.

After Turning on a Reference Clock to RX PLL

The reference clock source(s) and the power to the GTX transceiver(s) must be available
before configuring the FPGA. The reference clock must be stable before configuration
especially when using PLL-based clock sources (e.g., voltage controlled crystal oscillators).
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Components to be
Reset
Entire GTX RX
Entire GTX RX
Entire GTX RX
Entire GTX RX
RX PCS, RX Phase
Alignment
RX PCS
RX PCS, RX Phase
Alignment
RX CDR
A built-in reset sequencer automatically sets these situations by
RX CDR
setting RX_EN_IDLE_RESET_PH, RX_EN_IDLE_RESET_FR,
RX CDR
RX Elastic Buffer
RX CDR, then Either assert RXBUFRESET, or automatically reset by setting
RXBUFFER after
CDR is locked
RX elastic buffer is reset automatically after change in channel
RX Elastic Buffer
bonding mode by setting RX_EN_MODE_RESET_BUF to TRUE
PRBS Error Counter
Oversampler
RX Elastic Buffer RX elastic buffer is reset automatically after comma realignment
(optional)
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Recommended Reset
After configuration, the GTX RX is reset automatically
GTXRXRESET
GTXRXRESET
GTXRXRESET
RXRESET
RX RESET
RXRESET
RX_EN_IDLE_HOLD_CDR to TRUE
RXBUFRESET
RX_EN_IDLE_RESET_BUF = TRUE to enable the
RXBUFRESET sequence
PRBSCNTRESET
RXRESET
by setting RX_EN_REALIGN_RESET_BUF to TRUE
Virtex-6 FPGA GTX Transceivers User Guide
(1)
UG366 (v2.5) January 17, 2011