Enabling Comma Alignment; Configuring Comma Patterns - Xilinx Virtex-6 FPGA User Manual

Chapter 4: Receiver
X-Ref Target - Figure 4-22
The GTX transceiver includes an alignment block that can be programmed to align specific
commas to various byte boundaries, or to manually align data using attribute settings (see
Figure
can be bypassed to reduce latency if it is not needed.

Enabling Comma Alignment

To enable the comma alignment block, the RXCOMMADETUSE port is driven High.
RXCOMMADETUSE is driven Low to bypass the block completely for minimum latency.

Configuring Comma Patterns

To set the comma pattern that the block searches for in the incoming data stream, the
MCOMMA_10B_VALUE, PCOMMA_10B_VALUE, and COMMA_10B_ENABLE
attributes are used. The comma lengths depend on RX_DATA_WIDTH (see
page
values to allow partial pattern matching.
with COMMA_ENABLE to make a wildcarded comma for a 20-bit internal comma.
X-Ref Target - Figure 4-23
If COMMA_DOUBLE is TRUE, the MCOMMA and PCOMMA patterns are combined so
that the block searches for two commas in a row. The number of bits in the comma depends
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218
TX Parallel Data
Data0
Comma
Data1
Data2
Figure 4-22: Parallel Data View of Comma Alignment
4-22) SONET A1/A2 alignment is possible using comma double mode. The block
269). Figure 4-23 shows how the COMMA_10B_ENABLE masks each of the comma
MCOMMA_10B_VALUE
or
PCOMMA_10B_VALUE
0101111100
0001111111
COMMA_10B_ENABLE
Figure 4-23: Comma Pattern Masking
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RX Parallel Data
Non-aligned
Comma
Time
UG366_c4_20_051509
Figure 4-23 shows how a COMMA is combined
Pattern required
for comma detection
(x = don't care)
xxx1111100
Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Data
Data1
Data2
Table 4-56,
UG366_c4_21_051509