Precedence Between Channel Bonding And Clock Correction - Xilinx Virtex-6 FPGA User Manual

X-Ref Target - Figure 4-44
Master
Receives CB
Sequence
The Master waits MAX SKEW cycles before
triggering bonding, giving the slave time to
receive the sequence as well. The message
to perform channel bonding is sent using
the CHBONDO port.
The CHAN_BOND_LEVEL setting of the Master
determines how many cycles later the bonding
operation is executed. At this time, the Slave
Elastic Buffer pointers are moved so the
output is deskewed.
Figure 4-44: Channel Bonding Example (CHAN_BOND_*_MAX_SKEW = 2 and Master
CHAN_BOND_1_MAX_SKEW and CHAN_BOND_2_MAX_SKEW are used to set the
maximum skew allowed for channel bonding sequences 1 and 2, respectively. The
maximum skew range is 1 to 14. This range must always be less than one-half the
minimum distance (in bytes or 10-bit codes) between channel bonding sequences. This
minimum distance is determined by the protocol being used.

Precedence between Channel Bonding and Clock Correction

The clock correction (see
both perform operations on the pointers of the RX elastic buffer. Normally, the two circuits
work together without conflict, except when clock correction events and channel bonding
events occur simultaneously. In this case, one of the two circuits must take precedence. To
make clock correction a higher priority than channel bonding, CLK_COR_PRECEDENCE
must be set to TRUE. To make channel bonding a higher priority,
CLK_COR_PRECEDENCE must be set to FALSE.
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
SEQ1 D7 D6
D7 D6 D5
D10 D9 D8
D9 D8 SEQ1
D11 D10 D9
D10 D9 D8
RXCHANBONDLEVEL[2:0] = 1)
RX Clock Correction, page
www.xilinx.com
RX Channel Bonding
D5 D4 D3 D2
D4 D3 D2 D1
SEQ1 D7 D6 D5
D7 D6 D5 D4
D8 SEQ1 D7 D6
SEQ1 D7 D6 D5
Slave's New Elastic
Buffer Read Pointer
240) and channel bonding circuits
Master
D1
Elastic
Buffer
Slave
D0
Elastic
Buffer
Master
D4
Elastic
Buffer
Slave
Elastic
D3
Buffer
Master
D5
Elastic
Buffer
Slave
D4
Elastic
Buffer
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