Ports And Attributes - Xilinx Virtex-6 FPGA User Manual

Chapter 2: Shared Transceiver Features
within the Quad. In addition, they can be routed to the GTX transceivers in the north or
south neighboring Quads using the dedicated reference clock routing shown in
Each GTX transceiver can also select reference clocks from the Quad below (Q
from the NORTHREFCLKTX[0/1] and NORTHREFCLKRX[0/1] ports; reference clocks
from the Quad above (Q
SOUTHREFCLKRX[0/1] ports; reference clocks from the FPGA logic sourced from
PERFCLKTX and PERFCLKRX, or GREFCLKTX and GREFCLKRX.
The Xilinx software tools handle the complexity of the multiplexers and associated routing
for designs that require a single reference clock per GTX transceiver PLL. If dynamic
switching of reference clocks is required, the user must set the reference clock multiplexers
using the GTX TXPLLREFSELDY and RXPLLREFSELDY ports. The dedicated reference
clock routing between Quads is set by the Xilinx software tools in both single and multiple
reference clock modes.
Internal clock nets of the FPGA can provide reference clocks for the GTX transceiver by
connecting the output of a global clocking resource to the GTX PERFCLK or GREFCLK
port. Only one of these inputs can be connected at a time. These reference clock ports have
the lowest performance of the available clocking methods because FPGA clocking
resources can introduce jitter for operation at high data rates. Use of PERFCLK and
GREFCLK is reserved for internal test purposes only.

Ports and Attributes

Table 2-4
Table 2-4: GTX Clocking Ports
Port
GREFCLKRX
GREFCLKTX
MGTREFCLKRX[1:0]
MGTREFCLKTX[1:0]
NORTHREFCLKRX[1:0]
NORTHREFCLKTX[1:0]
PERFCLKRX
PERFCLKTX
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106
) sourced from the SOUTHREFCLKTX[0/1] and
(n+1)
defines the GTX clocking ports.
Dir Clock Domain
In Clock Internal FPGA logic clock. Reserved for internal testing
purposes only.
In Clock Internal FPGA logic clock. Reserved for internal testing
purposes only.
In Clock External jitter stable clock driven by IBUFDS_GTXE1 for the RX
PLL.
In Clock External jitter stable clock driven by IBUFDS_GTXE1 for the TX
PLL.
In Clock North-bound clocks from the Quad below.
In Clock North-bound clocks from the Quad below.
In Clock Internal FPGA logic clock. Reserved for internal testing
purposes only.
In Clock Internal FPGA logic clock. Reserved for internal testing
purposes only.
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Description
Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Figure 2-2.
) sourced
(n-1)