Rx Gearbox Block Synchronization - Xilinx Virtex-6 FPGA User Manual

Chapter 4: Receiver
X-Ref Target - Figure 4-46
RXHEADERVALID0
RXHEADER0
RXUSRCLK20
RXDATAVALID0
RXDATA0
Figure 4-46: RX Gearbox When Using 64B/66B Encoding and a 4-Byte Interface

RX Gearbox Block Synchronization

The 64B/66B and 64B/67B protocols depend on block synchronization to determine their
block boundaries. Block synchronization is required because all incoming data is
unaligned before block lock is achieved. The goal is to search for the valid synchronization
header by changing the data alignment. The RXGEARBOXSLIP input port is used to
change the gearbox data alignment so that all possible alignments can be checked. The
RXGEARBOXSLIP signal feeds back from the block synchronization state machine to the
RX Gearbox and tells it to slip the data alignment. This process of slipping and testing the
synchronization header repeats until block lock is achieved. When using the RX Gearbox,
a block synchronization state machine is required in the FPGA logic.
operation of a block synchronization state machine. The Virtex-6 FPGA GTX Transceiver
Wizard has example code for this type of module.
www.BDTIC.com/XILINX
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1 3 1
Header invalid every
other cycle.
www.xilinx.com
2 1 2 1
Data paused for 1 cycle.
Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
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UG366_c4_43_052110
Figure 4-47 shows the