Ports And Attributes - Xilinx Virtex-6 FPGA User Manual

Table 2-7: PLL Divider Attribute and Common Values
The Virtex-6 FPGA GTX transceiver allows the N1 divider to be set independently from
the PCS internal datapath width. This allows additional flexibility in reference clock
selection.

Ports and Attributes

Table 2-8
Table 2-8: PLL Ports
Port
PLLTXRESET
PLLRXRESET
TXPLLLKDET
RXPLLLKDET
TXPLLLKDETEN
RXPLLLKDETEN
TXPLLPOWERDOWN
RXPLLPOWERDOWN
Table 2-9
Table 2-9: PLL Attributes
Attribute
PMA_CFG
TX_CLK_SOURCE
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Factor
M TXPLL_DIVSEL_REF
RXPLL_DIVSEL_REF
N1 TXPLL_DIVSEL45_FB
RXPLL_DIVSEL45_FB
N2
D TXPLL_DIVSEL_OUT
RXPLL_DIVSEL_OUT
defines the PLL ports.
Clock
Dir
Domain
In Async These active-High PLL ports reset the dividers inside the PLL as well as
the PLL lock indicator block.
Out Async This active-High PLL frequency lock signal indicates that the PLL
frequency is within predetermined tolerance. The GTX transceiver and
its clock outputs are not reliable until this condition is met.
In Async This port enables the PLL lock detector and must always be tied High.
In Async These active-High PLL signals provide power down.
defines the PLL attributes.
Type
76-bit Reserved. Use only recommended values from the Virtex-6 FPGA GTX
Binary Transceiver Wizard.
String This attribute is the multiplexer select signal in
whether the TX PLL or the RX PLL supplies the clock for the TX datapath.
For applications where TX and RX have the same line rate with a small frequency
offset, using the RX PLL to supply both the TX and RX datapaths allows some
power savings.
Valid values are "TXPLL" and "RXPLL".
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Attribute Name
TXPLL_DIVSEL_FB
RXPLL_DIVSEL_FB
Description
Description
Valid Settings
1, 2
4, 5
2, 4, 5
1, 2, 4
Figure 2-8, which determines
PLL
115