Bus Interface; Selecting The External Configuration (Fabric Interface); Selecting The Internal Configuration; Clock Ratio - Xilinx RocketIO X User Manual

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Bus Interface

Selecting the External Configuration (Fabric Interface)

By using the signals TXDATAWIDTH[1:0] and RXDATAWIDTH[1:0], the fabric interface
can be determined.

Table 2-2: Selecting the External Configuration

Selecting the Internal Configuration

Table 2-3: Selecting the Internal Configuration

Clock Ratio

USRCLK2 clocks the data buffers. The ability to send parallel data to the transceiver at four
different widths requires the user to change the frequency of USRCLK2. This creates a
frequency ratio between USRCLK and USRCLK2. The falling edges of the clocks must
align. See

Table 2-4: Data Width Clock Ratios

46
RXDATAWIDTH/TXDATAWIDTH
2'b00
2'b01
2'b10
2'b11
RXINTDATAWIDTH/TXINTDATAWIDTH
2'b00
2'b01
2'b10
2'b11
Table 2-4.
Fabric Data Width
1 byte
2 byte
4 byte
8 byte
Notes:
1. Each edge of slower clock must align with falling edge of faster clock.
Chapter 2: Digital Design Considerations
Data Width
8/10 bit (1 byte)
16/20 bit (2 byte)
32/40 bit (4 byte)
64/80 bit (8 byte)
Internal Data Width
Frequency Ratio of USRCLK\USRCLK2
2-Byte Internal Data Width
(1)
1:2
1:1
(1)
2:1
N/A
www.xilinx.com
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Internal Bus
Requirements
16, 20 bit mode
16, 20 bit mode
16, 20, 32, 40 bit mode
32, 40 bit mode
16 bit
20 bit
32 bit
40 bit
4-Byte Internal Data Width
N/A
N/A
1:1
(1)
2:1
RocketIO™ X Transceiver User Guide
UG035 (v1.5) November 22, 2004