Signal Bga Breakout - Xilinx Virtex-6 FPGA User Manual

X-Ref Target - Figure 5-13

Signal BGA Breakout

The receiver, transmitter, and reference clock signals must be routed from the BGA pin
field to destinations on the PCB. The signal routing layers provide the routing resources for
this signal breakout. As shown in
can be routed using a microstrip on the top layer. These signals are routed to vias where the
signal is transitioned from the top microstrip layer to striplines on Layer 3. An advantage
to routing the signals from Layer 1 to Layer 3 is that the traces on both layers use the plane
on Layer 2 as the return current reference plane.
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
MGTAVCC 1.0V Island (Bottom)
Figure 5-13: Orientation between GTX Transceiver Power Islands and the
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MGTAVTT 1.2V Island (Top)
GTX Transceiver Region
Virtex-6
FPGA
Virtex-6 FPGA
Figure 5-14, the signals on the outer rows of BGA pins
Power Supply and Filtering
UG366_c5_13_051509
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