Rx Oversampling; Feature Description - Xilinx Virtex-6 FPGA User Manual

Chapter 4: Receiver

RX Oversampling

Feature Description

Each GTX transceiver includes built-in 5X oversampling to enable serial rates from 1/10
of the lower border of the frequency range of the RX PMA PLL up to 4/10th of the PLL. At
these low rates, the regular CDR must operate at five times the desired line rate to stay
within its operating limits. The digital oversampling circuit takes parallel data from the
SIPO at five times the desired line rate and uses the position of bit value transitions to
recover a clock. The transition points are also used to pick an optimal sampling point to
recover 4 bits of data from each set of 20 bits presented.
X-Ref Target - Figure 4-19
Note relevant to
1.
Each GTX transceiver can be configured for oversampling independent of the other
transceivers in a Quad. Configuring the GTX transceiver to use oversampling requires the
following steps:
•
•
•
The GTX Transceiver Wizard automatically configures the GTX transceiver and makes the
oversampling ports available when generating a GTX wrapper with oversampling
enabled.
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214
RXEQ
DFE
RX
CDR
RX-OOB
PMA
PLL
Divider
- Set to operate at 5x desired line rate
- Datapath is automatically set to 20 bits wide
Figure 4-19: GTX RX Block Diagram – Oversampling
Figure 4-19:
For more details about RX_DATA_WIDTH, refer to
Configuring the 5X line rate
Configuring the PCS internal datapath and clocks
Activating and operating the oversampling block
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Over-
SIPO
sampling
RX-PMA RX-PCS
- Takes data from 20-bit datapath at 5x rate
- Recovers clock at correct rate using digital algorithm
- Recovers data at the desired rate by extracting 4 bits for each 20 UI
- Remaining datapath uses width selected by RX_DATA_WIDTH
Virtex-6 FPGA GTX Transceivers User Guide
UG366_c4_17_120809
Table 4-56, page 269.
UG366 (v2.5) January 17, 2011
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