External Sequence Counter Operating Mode - Xilinx Virtex-6 FPGA User Manual

External Sequence Counter Operating Mode

As shown in
TXSEQUENCE[6:0], TXDATA[31:0], and TXHEADER[2:0] inputs. A binary counter must
exist in the user logic to drive the TXSEQUENCE input port. For 64B/66B encoding, the
counter increments from 0 to 32 and repeats from 0. For 64B/67B encoding, the counter
increments from 0 to 66 and repeats from 0. When using 64B/66B encoding, tie
TXSEQUENCE[6] to a logic 0 and tie the unused TXHEADER[2] to a logic 0. The sequence
counter increment ranges ({0 to 32}, {0 to 66}) are identical for both the 2-byte and 4-byte
interfaces. However, the counter must increment once every two TXUSRCLK2 cycles when
using a 2-byte interface and every TXUSRCLK2 cycle when using a 4-byte interface.
X-Ref Target - Figure 3-14
Due to the nature of the 64B/66B and 64B/67B encoding schemes, user data is held
(paused) during various sequence counter values. Data is then paused for two
TXUSRCLK2 cycles in 2-byte mode and for one TXUSRCLK2 cycle in 4-byte mode. Valid
data transfer is resumed on the next TXUSRCLK2 cycle. The data pause only applies to
TXDATA and not to TXHEADER.
•
•
Figure 3-15
external sequence counter mode, and 64B/66B encoding.
X-Ref Target - Figure 3-15
TXUSRCLK20
TXHEADER0
1
TXSEQUENCE0 - 24
TXDATA0
87964daa
www.BDTIC.com/XILINX
Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Figure 3-14, the external sequence counter operating mode uses the
TX Gearbox
(in GTX Transceiver)
Figure 3-14: TX Gearbox in External Sequence Counter Mode
64B/67B encoding: data is held (paused) for sequence counter values of 21, 44, and 65.
64B/66B encoding, data is held (paused) at counter value 31.
shows how a pause occurs at counter value 31 when using a 4-byte interface,
25 26 27 28 29
629a1470 8d14111a e3828711 8777acf1 7c580498
Figure 3-15: Pause at Sequence Counter Value 31
www.xilinx.com
TXDATA[15:0] or TXDATA[31:0]
TXHEADER[2:0]
TXSEQUENCE[6:0]
30 31 32 0 1
120459d5
4e1fea87 5714e976 523cd413
Pause for 1 USRCLK2 cycle. Data is ignored.
TX Gearbox
Design in FPGA Logic
Data Source
Pause
Sequence Counter
0-32 or 0-66
UG366_c3_04_051509
2 1
2 3 4 5 6
-
53365af5 4e658bf8 d3892141 c1a9308d
UG366_c3_05_051509
149