Ports And Attributes; Rx_Data_Width - Xilinx Virtex-6 FPGA User Manual

Table 4-59: RXUSRCLK2 Frequency Relationship to RXUSRCLK
The following rules about the relationships between clocks must be observed for
RXUSRCLK and RXUSRCLK2:
•
•
•
•
For details about placement constraints and restrictions on clocking resources (MMCM,
BUFGCTRL, IBUFDS_GTXE1, BUFG, etc.), refer to the Virtex-6 FPGA Clocking Resources
User Guide.

Ports and Attributes

Table 4-60
Table 4-60: FPGA RX Ports
Port
MGTREFCLKFAB[1:0]
RXCHARISK[3:0]
RXDATA[31:0]
RXDISPERR[3:0]
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011

RX_DATA_WIDTH

1-Byte 8, 10
2-Byte 16, 20
4-Byte 32, 40
RXUSRCLK and RXUSRCLK2 must be positive-edge aligned, with as little skew as
possible between them. As a result, low-skew clock resources (BUFGs and BUFRs)
should be used to drive RXUSRCLK and RXUSRCLK2.
describe the appropriate GEN_RXUSRCLK setting and RXUSRCLK2 frequency
requirements. In cases where RXUSRCLK is generated by the user, the designer must
ensure that RXUSRCLK and RXUSRCLK2 are positive-edge aligned.
If the channel is configured so the same oscillator drives the reference clock for the
transmitter and the receiver, TXOUTCLK can be used to drive RXUSRCLK and
RXUSRCLK2 in the same way that they are used to drive TXUSRCLK and
TXUSRCLK2. When clock correction is turned off or the RX buffer is bypassed, RX
phase alignment must be used to align the serial clock and the parallel clocks.
If separate oscillators are driving the reference clocks for the transmitter and receiver
on the channel, and clock correction is not used, RXUSRCLK and RXUSRCLK2 must
be driven by RXRECCLK, and the phase-alignment circuit must be used.
If clock correction is used, RXUSRCLK and RXUSRCLK2 can be sourced by
RXRECCLK or TXOUTCLK.
defines the FPGA RX ports.
Dir Clock Domain
Out Clock Reserved. Do not use this port.
Out RXUSRCLK2 When 8B/10B decoding is disabled, RXCHARISK is used to
extend the data bus for 10- and 20-bit RX interfaces.
Out RXUSRCLK2 The bus for transmitting data. The width of this port depends on
RX_DATA_WIDTH:
Out RXUSRCLK2 When 8B/10B decoding is disabled, RXDISPERR is used to
extend the data bus for 10- and 20-bit RX interfaces.
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RXUSRCLK2 Frequency
F
RXUSRCLK2
F
RXUSRCLK2
F
RXUSRCLK2
Description
RX_DATA_WIDTH = 8, 10: RXDATA[7:0] = 8 bits wide
RX_DATA_WIDTH = 16, 20: RXDATA[15:0] = 16 bits wide
RX_DATA_WIDTH = 32, 40: RXDATA[31:0] = 32 bits wide
FPGA RX Interface
= 2 x F
RXUSRCLK
= F
RXUSRCLK
= F / 2
RXUSRCLK
Table 4-58 and Table 4-59
271