Xilinx Virtex-6 FPGA User Manual page 196

Chapter 4: Receiver
X-Ref Target - Figure 4-12
P
Limiter
N
DFE_CFG[9:0]
RX Serial Clock
The DFE allows better compensation of transmission channel losses by providing a closer
adjustment of filter parameters than when using a linear equalizer. However, a DFE cannot
remove the pre-cursor of a transmitted bit. A linear equalizer allows pre-cursor and post-
cursor attenuation, but has only a coarse adaptor to the transmission channel
characteristic. The GTX DFE in the GTX RX is a discrete-time adaptive high-pass filter. The
TAP values of the DFE are the coefficients of this filter can be either set manually or by the
auto-calibration logic. The optimization criteria for the TAP values and the DFECLK delay
is the vertical eye opening. The DFETAPOVRD port switches off auto-calibration and
overrides the TAP values, and the DFEDLYOVRD port overrides the DFECLK delay.
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196
DFE
DFETAP1MONITOR[4:0]
DFETAP2MONITOR[4:0]
Automatic
DFETAP3MONITOR[3:0]
TAP
Value
Control
DFE
Controller
DFETAP4MONITOR[3:0]
Figure 4-12: DFE Conceptual View
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T
DFECLK
–TAP1
DFETAP1[4:0]
T
DFECLK
–TAP2
DFETAP2[4:0]
T
DFECLK
–TAP3
DFETAP3[3:0]
T
DFECLK
–TAP4
DFETAP4[3:0]
Virtex-6 FPGA GTX Transceivers User Guide
To CDR
DFETAP1MONITOR[4:0]
DFETAP2MONITOR[4:0]
DFETAP3MONITOR[3:0]
DFETAP4MONITOR[3:0]
UG366_c4_11_051509
UG366 (v2.5) January 17, 2011