Ports And Attributes - Xilinx Virtex-6 FPGA User Manual

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X-Ref Target - Figure 3-31
PISO
TX Serial Clock =
Data Rate / 2

Ports and Attributes

Table 3-31
Table 3-31: TX Configurable Driver Ports
Port
TXBUFDIFFCTRL[2:0]
TXDEEMPH
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Pre-cursor and post-cursor transmit pre-emphasis
Calibrated termination resistors
Pre-Driver
Pre-Driver
Pre-Driver
Figure 3-31: TX Driver Block Diagram
defines the TX configurable driver ports.
Dir Clock Domain
In Async Pre-driver Swing Control. The default is 3'b100 (nominal
value).
Do not modify this value.
In Async TX de-emphasis control for PCI Express PIPE interface. This
signal is mapped internally to TXPOSTEMPHASIS via attributes.
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Pre-Emphasis
Pad Driver
TXPREEMPHASIS[3:0]
Main
Pad Driver
TXDIFFCTRL[3:0]
Post-Emphasis
Pad Driver
TXPOSTEMPHASIS[4:0]
Description
0: 6.0 dB de-emphasis (TX_DEEMPH_0[4:0] attribute)
1: 3.5 dB de-emphasis (TX_DEEMPH_1[4:0] attribute)
TX Configurable Driver
MGTAVTT
nominal nominal
50Ω 50Ω
MGTTXP
MGTTXN
UG366_c3_19_072309
(1)
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