Tx Gearbox Operating Modes - Xilinx Virtex-6 FPGA User Manual

Chapter 3: Transmitter
header of the second 66-bit block, and 12 data bits from the second 66-bit block. As shown
in
X-Ref Target - Figure 3-13

TX Gearbox Operating Modes

The TX gearbox has two operating modes. The external sequence counter operating mode
must be implemented in user logic. The second mode uses an internal sequence counter.
The TX gearbox only supports 2-byte and 4-byte interfaces to the FPGA logic.
www.BDTIC.com/XILINX
148
Figure 3-13, the header bits are serialized first followed by the data bits.
Transmitted
Cycle 0
H
1
TXHEADER
Transmitted
Cycle 1
Transmitted
Cycle 2
Transmitted
Cycle 3
Transmitted
First
D
1
Cycle 4
H
1
TXHEADER
Figure 3-13: TX Gearbox Bit Ordering
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First
...
H H D D
1 0 15 14
Output of TX Gearbox
...
H D D
0 15 14
TXDATA
First
...
D D D D
1 0 15 14
Output of TX Gearbox
...
D D
15 14
TXDATA
First
...
D D D D
1 0 15 14
Output of TX Gearbox
...
D D
15 14
TXDATA
First
...
D D D D
1 0 15 14
Output of TX Gearbox
...
D D
15 14
TXDATA
...
D H H D D
0 1 0 15 14
Output of TX Gearbox
...
H D D
0 15 14
TXDATA
Virtex-6 FPGA GTX Transceivers User Guide
Transmitted
Last
D
2
D D
1 0
Transmitted
Last
D
2
D D
1 0
Transmitted
Last
D
2
D D
1 0
Transmitted
Last
D
2
D D
1 0
Transmitted
Last
D
4
D D
1 0
UG366_c3_03_051509
UG366 (v2.5) January 17, 2011