Pci Express Clocking Use Mode - Xilinx Virtex-6 FPGA User Manual

Chapter 3: Transmitter
Table 3-29: TX Fabric Clock Output Control Ports (Cont'd)
Port
TXRATE
TXRATEDONE
Table 3-30
Table 3-30: TX Fabric Clock Output Control Attributes
Attribute
TRANS_TIME_RATE
TX_EN_RATE_RESET_BUF
TXOUTCLK_CTRL
TXPLL_DIVSEL_OUT

PCI Express Clocking Use Mode

In most applications, TXOUTCLK port is used to clock the FPGA logic. TXOUTCLKPCS
via TXOUTCLK is used for the oversampling mode, and TXPLLREFCLK via TXOUTCLK
is used for the rest of the applications.
For PCI Express clocking, the use case is to route the reference clock from IBUFDS_GTXE1
directly to the FPGA user logic instead of through TXOUTCLK if the TX buffer is used, as
shown in
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170
Dir Clock Domain
In TXUSRCLK2 This port controls the setting for the TX serial clock divider for low
line rate support (see
combination with the TXPLL_DIVSEL_OUT attribute.
00: Let TXPLL_DIVSEL_OUT determine the D divider value
01: Set D divider to 4
10: Set D divider to 2
11: Set D divider to 1
Out TXUSRCLK2 The TXRATEDONE port is asserted High for one TXUSRCLK2 cycle
in response to a change on the TXRATE port. The
TRANS_TIME_RATE attribute defines the period of time between a
change on the TXRATE port and the assertion of TXRATEDONE.
defines the TX Fabric Clock Output Control block attributes.
Type
8-bit Reserved. Use only recommended values from the Virtex-6 FPGA GTX
Hex Transceiver Wizard.
This attribute determines when PHYSTATUS and TXRATEDONE are
asserted after a rate change.
Boolean When set to TRUE, this attribute enables automatic TX buffer reset during a
rate change event initiated by a change in TXRATE.
String This attribute is the multiplexer select signal in
determines which GTX transceiver internal clock is output to the FPGA logic
via the TXOUTCLK port. Valid settings are:
"TXOUTCLKPCS"
"TXOUTCLKPMA_DIV1"
"TXOUTCLKPMA_DIV2"
"TXPLLREFCLK_DIV1"
"TXPLLREFCLK_DIV2"
Integer This attribute controls the setting for the TX serial clock divider for low line
rate support (see
TXRATE = 00. Otherwise the D divider value is controlled by TXRATE.
Valid settings are:
1: Set the D divider to 1
2: Set the D divider to 2
4: Set the D divider to 4
Figure 3-29. However, if TX buffer is bypassed and compensation for voltage
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Description
Table 3-28). This input port is used in
Description
Table 3-28, page 168). This attribute is only valid when
Virtex-6 FPGA GTX Transceivers User Guide
Figure 3-28, page 167. It
UG366 (v2.5) January 17, 2011