Ports And Attributes; Rx_Buffer_Use; Boolean Use Or Bypass The Rx Elastic Buffer; True: Use The Rx Elastic Buffer (Normal Mode) - Xilinx Virtex-6 FPGA User Manual

Ports and Attributes

Table 4-43
Table 4-43: RX Elastic Buffer Ports
Port Dir
RXBUFRESET In
RXBUFSTATUS[2:0] Out
Notes:
1. If an RX elastic buffer overflow or an RX elastic buffer underflow condition occurs, the content of the RX elastic buffer becomes
invalid, and the RX elastic buffer needs re-initialization by asserting/deasserting RXBUFRESET.
Table 4-44
Table 4-44: RX Elastic Buffer Attributes
Attribute

RX_BUFFER_USE

RX_EN_IDLE_RESET_BUF
RX_FIFO_ADDR_MODE
RX_IDLE_HI_CNT
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
defines the RX elastic buffer ports.
Clock Domain
Async Resets the RX elastic buffer logic and re-initializes the RX elastic buffer.
RXUSRCLK2 Indicates the status of the RX elastic buffer as follows:
000: Nominal condition
001: Number of bytes in the buffer are less than CLK_COR_MIN_LAT
010: Number of bytes in the buffer are greater than
CLK_COR_MAX_LAT
101: RX elastic buffer underflow
110: RX elastic buffer overflow
defines the RX elastic buffer attributes.
Type
Boolean Use or bypass the RX elastic buffer.

TRUE: Use the RX elastic buffer (normal mode).

FALSE: Permanently bypass the RX elastic buffer (advanced feature). If
OVERSAMPLE_MODE is FALSE, RX phase alignment must be used
whenever the RX elastic buffer is bypassed.
Boolean Enable or disable the automatic RX elastic buffer reset.
TRUE: Enable the automatic RX elastic buffer reset when valid signals are
not present on the RXN/RXP inputs.
FALSE: Disable the automatic RX elastic buffer reset when valid signals are
not present on the RXN/RXP inputs.
String FULL: Enable the RX elastic buffer for clock correction and channel
bonding support. The maximum frequency is limited.
FAST: Enable the RX elastic buffer for phase compensation without clock
correction and channel bonding support. This mode is recommended for
high line rates.
4-bit Determines count value after which an assertion of reset due to
Binary RX_EN_IDLE_RESET_BUF is triggered after valid data is no longer present
on the RXP/RXN lines. Use the Virtex-6 FPGA GTX Transceiver Wizard
default.
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RX Elastic Buffer
Description
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Description
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