Pll Settings For Common Protocols - Xilinx Virtex-6 FPGA User Manual

Table 2-9: PLL Attributes (Cont'd)
Attribute
RX_CLK25_DIVIDER
TX_CLK25_DIVIDER

PLL Settings for Common Protocols

Table 2-10
Table 2-10: PLL Divider Settings for Common Protocols
Line Rate
Standard
[Gb/s]
4.25
Fibre Channel
2.125
(Single Rate)
1.0625
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Type
Integer This attribute is set to get an internal clock for the GTX channel:

1: CLKIN 25 MHz
2: 25 MHz < CLKIN
3: 50 MHz < CLKIN
4: 75 MHz < CLKIN
5: 100 MHz < CLKIN
6: 125 MHz < CLKIN
7: 150 MHz < CLKIN
8: 175 MHz < CLKIN
9: 200 MHz < CLKIN
10: 225 MHz < CLKIN
11: 250 MHz < CLKIN
12: 275 MHz < CLKIN
13: 300 MHz < CLKIN
14: 325 MHz < CLKIN
15: 350 MHz < CLKIN
16: 375 MHz < CLKIN
17: 400 MHz < CLKIN
18: 425 MHz < CLKIN
19: 450 MHz < CLKIN
20: 475 MHz < CLKIN
21: 500 MHz < CLKIN
22: 525 MHz < CLKIN
23: 550 MHz < CLKIN
24: 575 MHz < CLKIN
25: 600 MHz < CLKIN
26-32: Reserved
shows example PLL divider settings for several standard protocols.
Internal Data
PLL Frequency
Width
[16b/20b]
20b
20b
20b
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Description

50 MHz

75 MHz

100 MHz

125 MHz

150 MHz

175 MHz

200 MHz

225 MHz

250 MHz

275 MHz

300 MHz

325 MHz

350 MHz

375 MHz

400 MHz

425 MHz

450 MHz

475 MHz

500 MHz

525 MHz

550 MHz

575 MHz

600 MHz

625 MHz
REFCLK
(Typical)
[GHz]
[MHz]
2.125 212.5
2.125 106.25
2.125 106.25
Using Typical REFCLK
Frequency
N1 N2 D
5 2 1
5 4 2
5 4 4
PLL
M
1
1
1
117