Reference Clock; Overview - Xilinx Virtex-6 FPGA User Manual

Chapter 5: Board Design Guidelines
North/South Package Power Plane Prioritization
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Reference Clock

Overview

This section focuses on the selection of the reference clock source or oscillator. An oscillator
is characterized by:
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These characteristics are selection criteria when choosing an oscillator for a GTX
transceiver design.
voltage swing, peak- to-peak as used in the GTX transceiver portion of the Virtex-6 FPGA
Data Sheet.
X-Ref Target - Figure 5-5
+ V MGTREFCLKP
MGTREFCLKN
0
Figure 5-5: Single-Ended Clock Input Voltage Swing, Peak-to-Peak
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Depending on availability in the package, these Quads have equal priority.
Priority 1: MGT115
This Quad should be used if any of the GTX transceivers in the device are used in the
application. It contains the RCAL circuit that is required for the RX and TX internal
termination resistors.
Priority 2: MGT116/117/118
If present in the Virtex-6 device, these Quads are connected in the package to the same
power planes as MGT115, the north power plane bank. Therefore they have equal
priority. Because the north power planes need to be powered for MGT115, these Quads
are also powered; therefore they can be used without additional power supply
connections.
Priority 3: MGT110/111/112/113/114
These transceivers are connected to the south power planes. They should be used if all
Quads on the north power planes have already been utilized. If any of these Quads are
used, then all MGTAVCC_N and MGTAVTT_S pins need to be connected to the
appropriate power supply voltage.
Frequency range
Output voltage swing
Jitter (deterministic, random, peak-to-peak)
Rise and fall times
Supply voltage and current
Noise specification
Duty cycle and duty-cycle tolerance
Frequency stability
Figure 5-5
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illustrates the convention for the single-ended clock input
Virtex-6 FPGA GTX Transceivers User Guide
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UG366_c5_05_051509
UG366 (v2.5) January 17, 2011