Ports And Attributes - Xilinx Virtex-6 FPGA User Manual

Chapter 4: Receiver

Ports and Attributes

Table 4-34
Table 4-34: RX Comma Alignment and Detection Ports
Port
RXBYTEISALIGNED
RXBYTEREALIGN
RXCOMMADET
RXCOMMADETUSE
RXENMCOMMAALIGN
RXENPCOMMAALIGN
www.BDTIC.com/XILINX
222
defines the RX comma alignment and detection ports.
Dir Clock Domain
Out RXUSRCLK2 This signal from the comma detection and realignment circuit is
High to indicate that the parallel data stream is properly aligned
on byte boundaries according to comma detection.
There are several cycles after RXBYTEISALIGNED is asserted
before aligned data is available at the FPGA RX interface.
RXBYTEISALIGNED responds to plus comma alignment when
PCOMMA_
to minus comma alignment when MCOMMA_
TRUE.
Out RXUSRCLK2 This signal from the comma detection and realignment circuit
indicates that the byte alignment within the serial data stream
has changed due to comma detection.
Data can be lost when alignment occurs, which can cause data
errors (and disparity errors when the 8B/10B decoder is used).
Out RXUSRCLK2 This signal is asserted when the comma alignment block detects
a comma. The assertion occurs several cycles before the comma
is available at the FPGA RX interface.
In RXUSRCLK2 RXCOMMADETUSE activates the comma detection and
alignment circuit.
Bypassing the comma and alignment circuit reduces RX
datapath latency.
In RXUSRCLK2 Aligns the byte boundary when comma minus is detected.
In RXUSRCLK2 Aligns the byte boundary when comma plus is detected.
www.xilinx.com
Description
0: Parallel data stream not aligned to byte boundaries
1: Parallel data stream aligned to byte boundaries
DETECT is TRUE. RXBYTEISALIGNED responds
0: Byte alignment has not changed
1: Byte alignment has changed
0: Comma not detected
1: Comma detected
0: Bypass the circuit
1: Use the comma detection and alignment circuit
0: Disabled
1: Enabled
0: Disabled
1: Enabled
Virtex-6 FPGA GTX Transceivers User Guide
DETECT is
UG366 (v2.5) January 17, 2011