Ports And Attributes - Xilinx Virtex-6 FPGA User Manual

Note:
the north package power plane, as outlined in

Ports and Attributes

Table 4-1
Table 4-1: RX AFE Ports
Port
RXN
RXP (Pad)
Table 4-2
Table 4-2: RX AFE Attributes
Attribute
AC_CAP_DIS
CM_TRIM[1:0]
RCV_TERM_GND
RCV_TERM_VTTRX
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
MGTAVTT_* refers to MGTAVTT_S of the south package power plane and MGTAVTT_N of
defines the RX AFE ports.
Dir Clock Domain
In RX Serial Clock RXN and RXP are differential complements of one another forming
a differential receiver input pair. These ports represent pads. The
location of these ports must be constrained (see
page
defines the RX analog front end attributes.
Type
Boolean Bypasses the built-in AC coupling in the receiver.
TRUE: Built-in AC coupling capacitors are bypassed. DC coupling
to the receiver is possible.
FALSE: Built-in AC coupling capacitors are enabled.
See Chapter 5, Board Design
appropriate to add an additional external AC coupling capacitor
based on data rate or protocol.
See Use Modes – RX Termination
combinations.
2-bit Binary Adjusts the input common mode levels. These levels are automatically
set in the Virtex®-6 FPGA GTX Transceiver Wizard.
Boolean Activates the Ground reference for the receiver termination network.
The default for this attribute is TRUE for PCI Express designs.
Generally, for all other protocols, the default setting is FALSE.
TRUE: Ground reference for receiver termination activated.
FALSE: Ground reference for receiver termination disabled.
See Use Modes – RX Termination
combinations.
Boolean Activates the MGTAVTT_* reference for the receiver termination
network. The default for this attribute is FALSE for PCI Express
designs. For all other protocols, the default setting is TRUE. The
setting is FALSE when using AC coupling.
TRUE: MGTAVTT_* reference for receiver termination activated.
FALSE: MGTAVTT_* reference for receiver termination disabled.
See Use Modes – RX Termination
combinations.
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Figure 5-4, page
Description
41) and brought to the top level of the design.
Description
Guidelines, for details about when it is
for valid RX Termination
for valid RX Termination
for valid RX Termination
RX Analog Front End
277.
Implementation,
185