Gth Quad Initialization In Response To Completion Of Configuration - Xilinx Virtex-6 FPGA User Manual

Chapter 2: Shared Transceiver Features
Table 2-11: Reset Attributes (Cont'd)
Attribute
PCS_RESET_LANE0
PCS_RESET_LANE1
PCS_RESET_LANE2
PCS_RESET_LANE3
PCS_RESET_1_LANE0
PCS_RESET_1_LANE1
PCS_RESET_1_LANE2
PCS_RESET_1_LANE3

GTH Quad Initialization in Response to Completion of Configuration

Figure 2-6
configuration when the GTH transceiver is configured in full line rate mode (i.e.,
TXRATE<n>[1:0], SAMPLERATE<n>[2:0], and RXRATE<n>[1:0] ports are set to all zeros).
Follow these steps to initialize the GTH transceiver, when configured in full line rate mode:
1.
2.
3.
4.
5.
6.
60
Type
16-bit Hex This attribute controls the datapath resets. These bits vary by mode:
64B/66B: 0xF3FE
8B/10B: 0xFC5B
Raw: 0xFF3B
PRBS: 0xFFCE
Default: 0xFFFF
[15:12]: Reserved
[11]: Reset 64B/66B receive
[10]: Reset 64B/66B transmit
[9]: Reset 8B/10B receive
[8]: Reset 8B/10B transmit
[7]: Reset RX FIFO
[6]: Reset RX Raw FIFO
[5]: Reset PRBS checker
[4]: Reset PRBS generator
[3]: Reserved
[2]: Reset 8B/10B TX FIFO
[1]: Reset RX loopback FIFO
[0]: Reset 64B/66B and PRBS TX FIFO
16-bit Hex [15:2]: Reserved. Use the recommended values from the Virtex-6 FPGA
GTH Transceiver Wizard.
[1:0]: These bits control the datapath resets. They vary by mode:
64B/66B: 2'b10
8B/10B: 2'b00
Raw: 2'b00
PRBS: 2'b10
Default: 2'b11
shows the initialization sequence of the GTH Quad following completion of
Set PCS_MODE_LANE<n>[7:4] and PCS_MODE_LANE<n>[3:0] to the datapath
mode used in the application for RX and TX, respectively.
Set PCS_RESET_LANE<n> to the datapath mode used in the application.
Set PCS_RESET_1_LANE<n> to the datapath mode used in the application.
Set TXPOWERDOWN<n>[1:0] and RXPOWERDOWN<n>[1:0] to 2'b10.
After completion of configuration (GSR going High), wait for GTHINITDONE to go
High. The PLL is locked after GTHINITDONE is asserted.
Pulse TXBUFRESET for one TXUSERCLKIN clock cycle.
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Description
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010