Gtx Rx Reset In Response To Completion Of Configuration; Gtx Rx Reset In Response To Gtxrxreset Pulse - Xilinx Virtex-6 FPGA User Manual

Table 4-53: RX Initialization Attributes (Cont'd)
Attribute
RX_IDLE_HI_CNT[3:0]
RX_IDLE_LO_CNT[3:0]

GTX RX Reset in Response to Completion of Configuration

Figure 4-50
powered-up GTX transceiver. The same sequence is activated any time
RXPLLPOWERDOWN goes from High to Low during normal operation.
X-Ref Target - Figure 4-50
Note:
internal clock and certain configuration attributes. The estimate given in
the frequency of the internal clock is 50 MHz with default values for the configuration attributes.

GTX RX Reset in Response to GTXRXRESET Pulse

Figure 4-51
GTXRXRESET. GTXRXRESET acts as an asynchronous reset signal. The guideline for the
asynchronous GTXRXRESET pulse width is one period of the reference clock.
X-Ref Target - Figure 4-51
Note:
clock and certain configuration attributes. The estimate given in
frequency of the internal clock is 50 MHz with default values for the configuration attributes.
The entire GTX RX is affected by GTXRXRESET.
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Type
4-bit Programmable counters used in association with resetting the RX elastic
Binary buffer in response to the absence of valid data on the serial RX inputs.
Determines how long the serial RX inputs must remain in electrical idle
before the RX elastic buffer reset is asserted.
4-bit Programmable counters associated with deasserting the reset condition
Binary of the elastic buffer in response to the detection of valid data on the serial
RX inputs. Determines how long the serial RX inputs must have good
data (not be in electrical idle) before the RX elastic buffer reset is
deasserted.
shows the GTX RX reset following the completion of configuration of a
GSR
Wait
RX Reset FSM
RXRESETDONE
Figure 4-50: Receiver Reset After Configuration
The timing of the reset sequencer inside the GTX receiver depends on the frequency of an
is similar to Figure
GTXRXRESET
Idle
RX Reset FSM
RXRESETDONE
Figure 4-51: Receiver Reset after GTXRXRESET Pulse
The timing of the reset sequencer inside the GTX RX depends on the frequency of an internal
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Description
Reset in Progress
~120 µs
4-50, showing the reset occurring in response to a pulse on
Wait Reset in Progress
RX Initialization
UG366_c4_48_062209
Figure 4-50 assumes that
~120 µs
UG366_c4_47_062209
Figure 4-51 assumes that the
Idle
Idle
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