Rx Initialization; Functional Description; Ports And Attributes - Xilinx Virtex-6 FPGA User Manual

RX Initialization

Functional Description

The GTX RX must be reset before it can be used. There are three ways to reset the GTX RX:
1.
2.
3.
All the reset ports described in this section initiate the internal receiver reset state machines
when driven High. The internal reset state machines are held in the reset state until these
same reset ports are driven Low. The completion of these state machines is signaled
through the RXRESETDONE port.
Figure 4-49
X-Ref Target - Figure 4-49
When bypassing the TX buffer or the RX buffer, GTXRXRESET and PLLRXRESET must not
be tied High. Refer to
information.

Ports and Attributes

Table 4-52
Table 4-52: RX Initialization Ports
Port Dir
GTXRXRESET In
PLLRXRESET In
PRBSCNTRESET In
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Power up and configure the FPGA. Power-up reset is covered in this section.
Drive the GTXRXRESET port High to trigger a full asynchronous reset of the GTX RX.
Assert one or more of the individual reset signals on the block to reset a specific
subcomponent of the receiver. These resets are covered in detail in the sections for each
subcomponent (refer to Table 4-54, page
shows the GTX RX reset hierarchy.
After Configuration or GTXRXRESET or
PLLRXRESET
Figure 4-49: GTX RX Reset Hierarchy
TX Buffer Bypass, page 155
defines the RX initialization ports.
Clock Domain
Async This port is asserted High and then deasserted to start the full RX GTX
reset sequence. This sequence takes about 120 µs to complete, and
systematically resets all subcomponents of the GTX RX.
Async This port resets the RX PLL of the GTX RX.
RXUSRCLK2 This port resets the PRBS error counter.
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265).
Falling RXPLLPOWERDOWN
and RX Buffer Bypass, page 231
Description
RX Initialization
RXCDRRESET
RXRESET
RXBUFRESET
UG366_c4_46_061309
for more
261