Ports And Attributes; Use Models - Xilinx Virtex-6 FPGA User Manual

Chapter 4: Receiver

Ports and Attributes

Table 4-31
Table 4-31: Pattern Checker Ports
Port
PRBSCNTRESET
RXENPRBSTST[2:0]
RXPRBSERR
Table 4-32
Table 4-32: Pattern Checker Attributes
Attribute
RXPRBSERR_LOOPBACK
Table 4-33
Table 4-33: Pattern Checker Registers (Read Only)
Attribute
RX_PRBS_ERR_CNT

Use Models

To use the built-in PRBS checker, set RXENPRBSTST to match the PRBS pattern being sent
to the receiver. The RXENPRBSTST entry in
the PRBS checker is running, it attempts to find the selected PRBS pattern in the incoming
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defines the pattern checker ports.
Dir Clock Domain
In RXUSRCLK2 Reset PRBS error counter
In RXUSRCLK2 Receiver PRBS checker test pattern control. Only the following
settings are valid:
No checking is done for non-PRBS patterns. Single bit errors
cause bursts of PRBS errors as the PRBS checker uses data from
the current cycle to generate next cycle's expected data.
Out RXUSRCLK2 This non-sticky status output indicates that PRBS errors have
occurred.
defines the pattern checker attributes.
Type
1-bit Binary This attribute can only be controlled via the DRP. The address location
for this attribute is bit 8 of 0x2A.
When this attribute is set to 1, the RXPRBSERR bit is internally looped
back to TXPRBSFORCEERR of the same GTX transceiver. This allows
synchronous and asynchronous jitter tolerance testing without
worrying about data clock domain crossing.
When this attribute is set to 0, TXPRBSFORCEERR is forced onto the
TX PRBS.
defines the RX pattern checker registers.
Type
16-bit Binary PRBS error counter. This counter can be reset by asserting
PRBSCNTRESET. When there is an error(s) in incoming parallel data,
this counter increments by 1 and counts up to 0xFFFF. This error
counter can only be accessed via the DRP. The address for this counter
is 0x82.
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Description
000: Standard operation mode (PRBS check is off)
001: PRBS-7
010: PRBS-15
011: PRBS-23
100: PRBS-31
Description
Description
Table 4-31 shows the available settings. When
Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011