Sim_Gtxreset_Speedup - Xilinx Virtex-6 FPGA User Manual

Table 1-2: GTXE1 Simulation-Only Attributes (Cont'd)
Attribute
SIM_RXREFCLK_SOURCE
SIM_TX_ELEC_IDLE_LEVEL
SIM_TXREFCLK_SOURCE
SIM_VERSION

SIM_GTXRESET_SPEEDUP

The SIM_GTXRESET_SPEEDUP attribute can be used to shorten the simulated lock time of
the TX PMA PLL and the RX PMA PLL.
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Type
3-Bit Binary This attribute selects the reference clock source used to drive the RX
PMA PLL in simulation for designs where the RX PMA PLL is
always driven by the same reference clock source. The
RXPLLREFSELDY port must be set to 000 for this attribute to select
the reference clock source. For multi-rate designs that require the
reference clock source to be changed on the fly, the
RXPLLREFSELDY port is used to dynamically select the source
instead.
000: Selects the MGTREFCLKRX[0] port as the source
001: Selects the MGTREFCLKRX[1] port as the source
010: Selects the NORTHREFCLKRX[0] port as the source
011: Selects the NORTHREFCLKRX[1] port as the source
100: Selects the SOUTHREFCLKRX[0] port as the source
101: Selects the SOUTHREFCLKRX[1] port as the source
110: Reserved
111: Selects a clock from the FPGA logic which can be either port
GREFCLKRX or PERFCLKRX as the source
1-Bit Binary This attribute sets the value of TXN and TXP during simulation of
electrical idle. This attribute can be set to 0, 1, x, or z. The default for
this attribute is x.
3-Bit Binary This attribute selects the reference clock source used to drive the TX
PMA PLL in simulation for designs where the TX PMA PLL is
always driven by the same reference clock source. The
TXPLLREFSELDY port must be set to 000 for this attribute to select
the reference clock source. For multi-rate designs that require the
reference clock source to be changed on the fly, the
TXPLLREFSELDY port is used to dynamically select the source
instead.
000: Selects the MGTREFCLKTX[0] port as the source
001: Selects the MGTREFCLKTX[1] port as the source
010: Selects the NORTHREFCLKTX[0] port as the source
011: Selects the NORTHREFCLKTX[1] port as the source
100: Selects the SOUTHREFCLKTX[0] port as the source
101: Selects the SOUTHREFCLKTX[1] port as the source
110: Selects the RX recovered clock from the RX channel as the
source
111: Selects a clock from the FPGA logic that can be either the
GREFCLKTX or the PERFCLKTX port as the source
Real This attribute selects the simulation version to match different
steppings of silicon. The default for this attribute is 1.0.
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Description
Simulation
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