Rx Channel Bonding; Functional Description; Ports And Attributes - Xilinx Virtex-6 FPGA User Manual

RX Channel Bonding

Functional Description

The RX elastic buffer can also be used for channel bonding. Channel bonding cancels out
the skew between GTX transceiver lanes by using the RX elastic buffer as a variable latency
block. The transmitter sends a pattern simultaneously on all lanes, which the channel
bonding circuit uses to set the latency for each lane so that data is presented without skew
at the FPGA RX interface.
Figure 4-38
X-Ref Target - Figure 4-38

Ports and Attributes

Table 4-48
Table 4-48: RX Channel Bonding Ports
Port
RXCHANBONDSEQ
RXCHANISALIGNED
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
shows a conceptual view of channel bonding.
RX Data is Two Clock Cycles
Ahead of GTX1 Data
RX Data is Two Clock Cycles
Behind GTX0 Data
Figure 4-38: Channel Bonding Conceptual View
defines the RX channel bonding ports.
Dir Clock Domain
Out RXUSRCLK2
Out RXUSRCLK2
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64 Element Elastic Buffer
(Set to Four Cycles of Latency by
Channel Bonding Controller)
64 Element Elastic Buffer
(Set to Two Cycles of Latency by
Channel Bonding Controller)
Description
This port goes High when RXDATA contains the start of a
channel bonding sequence.
This signal from the RX elastic buffer goes High to indicate that
the channel is properly aligned with the master transceiver
according to observed channel bonding sequences in the data
stream. This signal goes Low if an unaligned channel bonding
sequence is detected, indicating that channel alignment was
lost.
RX Channel Bonding
Deskewed Data
GTX0 (Master)
Deskewed Data
GTX1 (Slave)
UG366_c4_35_051509
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