Ports And Attributes - Xilinx Virtex-6 FPGA User Manual

Chapter 4: Receiver
the CDR to be adjusted so that there is no significant phase difference between XCLK and
RXUSRCLK.
X-Ref Target - Figure 4-31
RX Serial Clock
D
RX
F
EQ
E
RX
SIPO
CDR
RX
OOB
Shared
PMA
PLL
Divider
From Shared PMA PLL
RX-PMA
Note:
certain system-level conditions.
To ensure that the RXRECCLK output port operates at the desired frequency in RX buffer
bypass mode, all of these conditions must be met:
•
•
•
•
For transceivers that are not instantiated in the user design, the ISE software, version 12.1
or later, automatically ensures that the RXRECCLK performance is preserved for future
use. MGTAVCC must be supplied to these transceivers. Refer to
Transceivers, page 276

Ports and Attributes

Table 4-40
www.BDTIC.com/XILINX
232
PMA Parallel Clock
(XCLK)
Comma
Detect
RX
Over-
and
Polarity
sampling
Align
PRBS
Check
RX Elastic Buffer Bypassed
RX-PCS
After phase alignment:
- SIPO parallel clock phase matches RXUSRCLK phase
- No phase difference between XCLK and RXUSRCLK
Figure 4-31: Using Phase Alignment
Bypassing the RX buffer is an advanced feature. RX buffer bypass can operate only under
Receiver reference clock must always be toggling
RXPOWERDOWN[0] and RXPOWERDOWN[1] must be tied Low
RXPLLPOWERDOWN must be tied Low
GTXRXRESET and PLLRXRESET must not be tied High
for more information.
defines the RX buffer bypass ports.
www.xilinx.com
RX
10B/8B
Elastic
Decoder
Buffer
Loss of Sync
RX Status Control
Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
RX Interface
Parallel Clock
(RXUSRCLK2)
PCS Parallel
Clock
(RXUSRCLK)
RX
Gearbox
FPGA
RX
Interface
UG366_c4_28_051509
Managing Unused GTX