Sim_Version; Sim_Tx_Elec_Idle_Level; Implementation; Functional Description - Xilinx Virtex-6 FPGA User Manual

SIM_VERSION

The SIM_VERSION attribute selects the simulation version to match different steppings of
silicon. The default for this attribute is 1.0.

SIM_TX_ELEC_IDLE_LEVEL

The SIM_TX_ELEC_IDLE_LEVEL attribute sets the value of the transceiver's differential
transmitter output pair TXN and TXP during simulation of electrical idle. This attribute
can be set to 0, 1, x, or z. The default for this attribute is x.

Implementation

Functional Description

This section provides the information needed to map Virtex-6 FPGA GTX transceivers
instantiated in a design to device resources, including:
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It is a common practice to define the location of GTX transceivers early in the design
process to ensure correct usage of clock resources and to facilitate signal integrity analysis
during board design. The implementation flow facilitates this practice through the use of
location constraints in the UCF.
While this section describes how to instantiate GTX clocking components, the details of the
different GTX transceiver clocking options are discussed in
page
The position of the GTX transceiver is specified by an XY coordinate system that describes
the column number and its relative position within that column. In current members of the
Virtex-6 family, all GTX transceivers are located in a single column along one side of the
die.
The transceiver with the coordinates "X0Y0" is for a given device/package combination
always located at the lowest position of the lowest available bank. For the combination of
a package with a large pin count (for example, 1759) and a smaller device (for example,
XC6VLX240T), transceivers at higher or lower banks are not available.
There are two ways to create a UCF for designs that utilize the GTX transceiver. The
preferred method is to use the Virtex-6 FPGA GTX Transceiver Wizard (see
GTX Transceiver Wizard, page
that configure the transceivers and contain placeholders for GTX placement information.
The UCFs generated by the Wizard can then be edited to customize operating parameters
and placement information for the application.
The second approach is to create the UCF by hand. When using this approach, the designer
must enter both configuration attributes that control transceiver operation as well as tile
location parameters. Care must be taken to ensure that all of the parameters needed to
configure the GTX transceiver are correctly entered.
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
The location of the GTX transceiver on the available device and package
combinations.
The pad numbers of external signals associated with each GTX transceiver.
How GTX transceiver and clocking resources instantiated in a design are mapped to
available locations with a user constraints file (UCF).
102.
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36). The Wizard automatically generates UCF templates
Implementation
Reference Clock Selection,
Virtex-6 FPGA
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