Txusrclk And Txusrclk2 Generation - Xilinx Virtex-6 FPGA User Manual
Gtx transceivers
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When the 8B/10B encoder is bypassed and the TX_DATA_WIDTH is 10, 20, or 40, the
TXCHARDISPMODE and TXCHARDISPVAL ports are used to extend the TXDATA port
from 8 to 10 bits, 16 to 20 bits, or 32 to 40 bits.
the 8B/10B encoder is disabled.
Table 3-2: TX Data Transmitted when 8B/10B Encoder Bypassed
3
3
3
3
3
9
8
7
6
5
Data
Transmitted
TXUSRCLK and TXUSRCLK2 Generation
The FPGA TX interface includes two parallel clocks: TXUSRCLK and TXUSRCLK2.
TXUSRCLK is the internal clock for the PCS logic in the GTX transmitter. The required rate
for TXUSRCLK depends on the internal datapath width of the GTXE1 primitive and the TX
line rate of the GTX transmitter.
TXUSRCLK.
TXUSRCLK can be generated internally to the GTX transceiver. This functionality is
controlled by the GEN_TXUSRCLK attribute.
the TXUSRCLK can be generated internally by the GTX transceiver. In these cases, the
TXUSRCLK port must be tied Low.
Table 3-3: TXUSRCLK Internal Generation Configurations
Notes:
1. For single lane protocols such as 1 Gb/s Ethernet, "GTX Lanes in Channel" is 1. For multiple lane
TXUSRCLK2 is the main synchronization clock for all signals into the TX side of the GTX
transceiver. Most signals into the TX side of the GTX transceiver are sampled on the
positive edge of TXUSRCLK2. TXUSRCLK2 and TXUSRCLK have a fixed-rate relationship
based on the TX_DATA_WIDTH setting.
TXUSRCLK2 and TXUSRCLK per TX_DATA_WIDTH values.
www.BDTIC.com/XILINX
Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
< < Data transmission order is right to left < <
3
3
3
3
3
2
2
2
2
2
4
3
2
1
0
9
8
7
6
5
TXUSRCLK Rate
TX_DATA_WIDTH
1-Byte
8, 10
2-Byte
16, 20
4-Byte
32, 40
protocols like XAUI, "GTX Lanes in Channel" is 2 or more.
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Table 3-2
2
2
2
2
2
1
1
1
1
1
4
3
2
1
0
9
8
7
6
5
Equation 3-1
shows how to calculate the required rate for
Line Rate
=
------------------------------------------------------------------- -
Internal Datapath Width
Table 3-3
GTX Lanes in Channel
2 or more
1 or more
1 or more
Table 3-4
shows the relationship between
FPGA TX Interface
shows the data transmitted when
1
1
1
1
1
9 8 7 6 5 4 3 2 1 0
4
3
2
1
0
Equation 3-1
describes the situations in which
(1)
GEN_TXUSRCLK
1
TRUE
FALSE
TRUE
FALSE
129
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