Gtx Tx Latency - Xilinx Virtex-6 FPGA User Manual

Appendix C: Low Latency Design

GTX TX Latency

Figure C-2
for more details on the GTX TX blocks.
X-Ref Target - Figure C-2
TX Serial Clock
7
TX TX
TX
OOB Pre/
PISO
Driver
and Post
PCIe Emp
6 5
PLL
TX PMA
Table C-1
of the transmitter section of the GTX transceiver. The values in the Block Number column
correspond to the circled numbers in
Table C-1: GTX TX Latency
Block Block
Number Name
FPGA TX
1
Interface
8B/10B
2
Encoder
3 TX Buffer
PMA +
4+5+6+7
Interface
Total TX Latency
www.BDTIC.com/XILINX
316
shows a detailed block diagram of the GTX TX. Refer to
PMA Parallel Clock (XCLK)
Polarity
4
TX PCS
To RX Parallel Data
(Near-End PCS
Loopback)
Figure C-2: GTX TX Block Diagram
defines the latency for the specific functional blocks or group of functional blocks
TX_DATA_WIDTH = 8/10
0.5 cycle
TXENC8B10BUSE = 0
0 cycles
TX_BUFFER_USE = FALSE
1 cycle
Minimum
3.5 cycles
www.xilinx.com
PCS Parallel Clock (TXUSRCLK)
PCIe
Beacon
SATA Pattern
OOB Generator
3
Phase
Adjust
FIFO
From RX Parallel
Data (Far-End PMA
Loopback)
Figure C-2.
TX Latency (TXUSRCLK)
TX_DATA_WIDTH = 16/20
1 cycle
2 cycles
Virtex-6 FPGA GTX Transceivers User Guide
TX Overview, page 127
FPGA Parallel
(TXUSRCLK2)
TX Gearbox
TX PIPE
Control
FPGA TX
8B/10B
Interface
Encoder
2
1
From RX Parallel
Data (Far-End PCS
Loopback)
UG366_aC_02_110110
TX_DATA_WIDTH = 32/40
2 cycles
TXENC8B10BUSE = 1
1 cycle
TX_BUFFER_USE = TRUE
2 cycles
Maximum
7 cycles
UG366 (v2.5) January 17, 2011
Clock