Ports And Attributes - Xilinx Virtex-6 FPGA User Manual

Ports and Attributes

Table 4-11
Table 4-11: RX Equalizer Ports
Port
DFECLKDLYADJ[5:0]
DFECLKDLYADJMON[5:0]
DFEDLYOVRD
DFEEYEDACMON[4:0]
DFESENSCAL[2:0]
DFETAP1[4:0]
DFETAP1MONITOR[4:0]
DFETAP2[4:0]
DFETAP2MONITOR[4:0]
DFETAP3[3:0]
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
defines the RX equalizer ports.
Dir Clock Domain
In RXUSRCLK2 DFE clock delay adjust override for each transceiver.
This DFE is automatically calibrated for optimal performance
by a built-in state machine. This override value is only
accepted when DFEDLYOVRD is 1.
Out RXUSRCLK2 DFE clock delay calibration result monitor for each transceiver.
In RXUSRCLK2 Override enable for the DFE clock delay adjustment.
When switching from override mode to the optimized mode
dynamically, always toggle GTXRXRESET.
Out RXUSRCLK2 Averaged Vertical Eye Height (voltage domain) used by the
DFE as an optimization criterion.
Out RXUSRCLK2 Sampler sensitivity self-calibration after the reset.
In RXUSRCLK2 DFE tap 1 weight value control for each transceiver (5-bit
resolution).
Out RXUSRCLK2 DFE tap 1 weight value monitor for each transceiver (5-bit
resolution).
In RXUSRCLK2 DFE tap 2 weight value control for each transceiver (4-bit
resolution plus 1-bit sign). For example, –2 is represented as
1 0010.
Out RXUSRCLK2 DFE tap 2 weight value monitor for each transceiver (4-bit
resolution plus 1-bit sign). For example, –2 is represented as
1 0010.
In RXUSRCLK2 DFE tap 3 weight value control for each transceiver (3-bit
resolution plus 1-bit sign). For example, –2 is represented as
1 010.
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Description
000000: Phase difference between the bit serial sample
clock and the DFECLK is 0°.
111111: Phase difference between the bit serial sample
clock and the DFECLK is 90°.
0: Use the optimized DFE clock delay calibration value
(recommended).
1: Override the DFE clock delay calibration state machine
with the value provided by DFECLKDLYADJ[5:0]. The
optimized DFE clock delay calibration is done when
GTXRXRESET is deasserted.
11111: Indicates approximately 200 mV
opening.
000: Lowest offset
111: Highest offset
RX Equalizer
of internal eye
PPD
197