Ac Coupled Reference Clock; Unused Reference Clocks; Reference Clock Power; Reference Clock Toggling - Xilinx Virtex-6 FPGA User Manual

X-Ref Target - Figure 5-10

AC Coupled Reference Clock

AC coupling of the oscillator reference clock output to the Quad reference clock inputs
serves multiple purposes:
•
•
•
To minimize noise and power consumption, external AC coupling capacitors between the
sourcing oscillator and the Quad dedicated clock reference clock input pins are required.

Unused Reference Clocks

It is recommended to connect the unused differential input pin clock pair to ground or
leave both MGTREFCLKP and MGTREFCLKN floating.

Reference Clock Power

MGTAVCC powers the GTX transceiver reference clock input circuit. Excessive noise on
this supply has a negative impact on the performance of any Quad that uses the reference
clock from this circuit.

Reference Clock Toggling

An actively toggling reference clock must be supplied to any transceiver that bypasses the
TX or RX buffer at any time. Refer to
page 231

Power Supply and Filtering

Overview

The Quad requires two analog power supplies: MGTAVCC at a nominal voltage level of
1.0 V
analog power supplies are tied to a plane in the package. Some packages contain two
planes (a north plane and a south plane) for each of the analog power supplies. See
www.BDTIC.com/XILINX
Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
LVPECL Oscillator
Figure 5-10: Interfacing an LVPECL Oscillator to a GTX Transceiver Reference
DC current is blocked between the oscillator and the Quad dedicated clock input pins
(which reduces the power consumption of both parts as well)
Common mode voltage independence
The AC coupling capacitor forms a high-pass filter with the on-chip termination that
attenuates a wander of the reference clock
for more information.
, and MGTAVTT at a nominal voltage level of 1.2 V
DC
www.xilinx.com
0.01 µF
0.01 µF
240Ω 240Ω
Clock Input
TX Buffer Bypass, page 155
Power Supply and Filtering
Internal to Virtex-6 FPGA
GTX Transceiver
Reference Clock
Input Buffer
UG366_c5_10_051809
and RX Buffer Bypass,
. The pins for each of these
DC
Analog
283