Chapter 4: Receiver
RX 8B/10B Decoder
Functional Description
Many protocols require receivers to decode 8B/10B data. 8B/10B is an industry standard
encoding scheme that trades two bits of overhead per byte for improved performance.
The GTX transceiver includes an 8B/10B decoder to decode RX data without consuming
FPGA resources. The decoder includes status signals to indicate errors and incoming
control sequences. If decoding is not needed, the block can be disabled to minimize latency.
8B/10B Decoder Bit and Byte Order
8B/10B requires bit a0 to be received first, but the GTX transceiver always receives the
right-most bit first. Consequently, the 8B/10B decoder is designed to automatically reverse
the bit order of received data before decoding it. Similarly, because the GTX transceiver
receives the right-most bit first, when a 2-byte interface is used, the first byte received (byte
0) is presented on RXDATA[7:0], and the second byte is presented on RXDATA[15:8].
When a 4-byte interface is used, the first received byte is presented on RXDATA[23:16], and
the fourth byte is presented on RXDATA[31:24].
10-bit data to 8-bit values.
X-Ref Target - Figure 4-29
H
G
F
E
1
1
1
1
RXDATA
15
14
13
12
j
h
g
f
i
1
1
1
1
1
Received
Last
H 3 G 3 F 3 E 3 D 3 C 3 B 3 A 3 H 2 G 2 F 2 E 2 D 2 C 2 B 2 A 2
RXDATA
31
30
29
28
27
26
j
h
g
f
i
e
d
3
3
3
3
3
3
3
Received
Last
www.BDTIC.com/XILINX
228
RX_DATA_WIDTH = 20
D
C
B
A
H
G
1
1
1
1
0
0
11
10
9
8
7
6
8B/10B
e
d
c
b
a
j
h
g
1
1
1
1
1
0
0
0
25
24
23
22
21
20
19
c
b
a
j
h
g
f
i
e
d
3
3
3
2
2
2
2
2
2
2
Figure 4-29: RX Interface with 8B/10B Decoding
www.xilinx.com
Figure 4-29
F
E
D
C
B
A
0
0
0
0
0
0
5
4
3
2
1
0
f
i
e
d
c
b
a
0
0
0
0
0
0
0
Received
First
RX_DATA_WIDTH = 40
H 1 G 1 F 1 E 1 D 1 C 1 B 1 A 1 H 0 G 0 F 0 E 0 D 0 C 0 B 0 A 0
18
17
16
15
14
13
12
11
8B/10B
c
b
a
j
h
g
f
i
e
2
2
2
1
1
1
1
1
1
Virtex-6 FPGA GTX Transceivers User Guide
shows how the decoder maps
RX_DATA_WIDTH = 10
H
G
F
E
D
C
0
0
0
0
0
0
7
6
5
4
3
2
8B/10B
j
h
g
f
i
e
d
0
0
0
0
0
0
0
Received
Received
Last
10
9
8
7
6
5
4
3
d
c
b
a
j
h
g
f
i
e
1
1
1
1
0
0
0
0
0
0
UG366 (v2.5) January 17, 2011
B
A
0
0
1
0
c
b
a
0
0
0
First
2
1
0
d
c
b
a
0
0
0
0
Received
First
UG366_c4_26_051509