Rx Buffer Bypass; Functional Description - Xilinx Virtex-6 FPGA User Manual

Table 4-39
Table 4-39: RX Decoder Attributes
Attributes
DEC_MCOMMA_DETECT
DEC_PCOMMA_DETECT
DEC_VALID_COMMA_ONLY
RX_DATA_WIDTH
RX_DECODE_SEQ_MATCH

RX Buffer Bypass

Functional Description

Bypassing the RX buffer is an advanced feature of the Virtex-6 FPGA GTX transceivers. RX
buffer bypass can operate only under certain system-level conditions. The RX
phase-alignment circuit is used to adjust the phase difference between the PMA parallel
clock domain (XCLK) and the RXUSRCLK domain when the RX buffer is bypassed.
Figure 4-34, page 238
the trade-offs between the buffer and the buffer bypass modes.
The RX elastic buffer can be bypassed to reduce latency when RXRECCLK is used to source
RXUSRCLK and RXUSRCLK2. When the RX elastic buffer is bypassed, latency through the
RX datapath is low and deterministic, but clock correction and channel bonding are not
available.
Figure 4-31
phase alignment, there is no guaranteed phase relationship between the parallel clock
generated from the recovered clock in the CDR circuit (XCLK) and the parallel clocks from
the FPGA logic (RXUSRCLK and RXUSRCLK2). Phase alignment causes RXRECCLK from
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
defines the RX decoder attributes.
Type
Boolean Enables detection of negative 8B/10B commas:
TRUE: RXCHARISCOMMA is asserted when RXDATA is a
negative 8B/10B comma
FALSE: RXCHARISCOMMA does not respond to negative
8B/10B commas
Boolean Enables detection of positive 8B/10B commas:
TRUE: RXCHARISCOMMA is asserted when RXDATA is a
positive 8B/10B comma
FALSE: RXCHARISCOMMA does not respond to positive 8B/10B
commas
Boolean Limits the set of commas to which RXCHARISCOMMA responds:
TRUE: RXCHARISCOMMA is asserted only for K28.1, K28.5, and
K28.7 (see 8B/10B K character table in
FALSE: RXCHARISCOMMA responds to any positive or negative
8B/10B comma, depending on the settings for
DEC_MCOMMA_DETECT and DEC_PCOMMA_DETECT
Integer Selects PCS data width mode between the values of 8, 16, 32, 10, 20,
and 40. If 8B/10B is used, this attribute must be set to a multiple of 10
{10, 20, 40} even though only a multiple of 8 {8, 16, 32} RXDATA bits
come out to the FPGA logic. RXUSRCLK and RXUSRCLK2 clock
frequencies also need to be set correctly.
Boolean Selects whether a datastream is coming out of the Comma Detection
and Realign block (FALSE) or the 8B/10B decoder output (provided
that RXDEC8B10BUSE is also High) should be used for channel
bonding and clock correction sequences (TRUE).
shows the XCLK and USRCLK domains.
shows how phase alignment allows the RX elastic buffer to be bypassed. Before
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RX Buffer Bypass
Description
Appendix A)
Table 4-42, page 238 shows
231